Cadence delivers new verification IP

1 min read

Cadence Design Systems is making available10 new Verification IP (VIP) solutions that will allow engineers to efficiently verify their designs to meet the specifications for the latest standards protocols.

The expansion of the Cadence VIP portfolio will provide support for customers developing SoCs and microcontrollers for automotive, hyperscale data centre and mobile applications, including with CXL, HBM3, TileLink and MIPI CSI 2sm 3.0.

Cadence VIP are part of the Cadence Verification Suite which is comprised of core engines and verification fabric technologies that increase verification throughput and design quality, addressing verification requirements for a wide variety of applications and vertical segments.

The new Cadence VIP offer customers a comprehensive verification solution for the most complex protocols. Customers have access to a consistent API across all VIP with complete bus functional models (BFMs), integrated protocol checks and coverage models, ensuring they can rapidly adopt the appropriate VIP needed for their design.

The new VIP solutions support multiple application areas and specifications, including:

Hyperscale data centre:

  • CXL – Compute Express Link
  • HBM3
  • Ethernet 802.3ck


  • CSI-2 3.0
  • MIPI I3C 1.1

Consumer and mobile:

  • TileLink
  • eUSB2
  • UFS 3.1
  • MIPI RFFEsm v3.0

In addition, all Cadence VIP include Cadence TripleCheck technology, which provides users with a specification-compliant verification plan that is linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification.

“The requirements for higher bandwidth, lower power and more effective cache coherency management are growing exponentially, driving a new set of protocols to address them,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “With these 10 new VIP, Cadence is providing customers with smart verification solutions that ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, enabling increased verification throughput and the fastest path to IP, SoC and microcontroller verification closure.”