Cadence announces the Tempus Power Integrity Solution

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Cadence Design Systems has unveiled the Tempus Power Integrity Solution, the first comprehensive static timing/signal integrity analysis and power integrity analysis tool, which enables engineers to create more reliable designs at 7nm and below.

The Tempus Power Integrity Solution integrates the widely used Cadence Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution.

Customers using the new tool will be able to significantly lower IR drop design margins without compromising signoff quality, improving power and area. Early use cases have shown that Tempus correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improved the maximum frequency in silicon by up to 10%, as well as reducing the engineering workload and speeding design closure.

The tool’s other key benefits include:

Smaller IR drop margins to improve power and area: Intelligent activity generation and direct calculation of the timing impact of IR drop reduces the need for larger safety margins, optimising power and area.

Comprehensive signoff coverage: Vectorless activity generation automatically develops activity vectors for full coverage while also exploring potential failure scenarios on voltage- sensitive paths, improving signoff IR drop analysis reliability.

Proprietary vectorless-based algorithm to identify voltage-sensitive paths: Sensitivity analysis combined with proprietary algorithms developed through machine learning (ML) techniques efficiently identify critical paths most likely impacted by IR drop. Tempus Power Integrity’s methods ensure a high degree of IR drop analysis coverage without requiring extensive, time-consuming vectors.

Find and fix potential IR drop failures: Visibility into voltage-sensitive high-risk failure scenarios allows designers to catch potential problems early in the design cycle and fix them automatically.

"Our relentless focus on creating deep integrations with our complete RTL-to-GDS solution has made it possible to deliver new capabilities that help customers achieve design excellence and in a way that’s unprecedented in the industry,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence.

“The Tempus Power Integrity Solution resolves the issue of timing being dependent on IR drop, and vice-versa. Additionally, our combined signoff engines provide customers with a solution that’s faster and easier to use.”