The platform enables seamless integration of RF-to-sub-THz CMOS and III/V chiplets on a single carrier, achieving a record-low insertion loss of just 0.73dB/mm at frequencies up to 325GHz, and paves the way for compact, low-loss, and scalable next-generation RF and mixed-signal systems.
In pursuit of advanced applications, whether wireless data centres or high-resolution automotive radar to pluggable optical transceivers and ultra-high-speed wireless USB solutions for short-range device-to-device communications, there is an acceleration towards mmWave (30-100GHz) and sub-THz (100-300GHz) frequency bands.
However, unlocking the potential of these higher frequencies requires components that combine the high output power and drive capabilities of III/V materials with the scalability and cost-efficiency of CMOS technology, all integrated on a single carrier.
This is where chiplet-based heterogeneous systems, built on RF silicon interposer technology, can make the difference, enabling the seamless integration of digital and RF components.
At last year’s IEDM, imec reported a breakthrough in the hetero-integration of InP chiplets on a 300mm RF Si interposer, at frequencies up to 140GHz. Now, at ECTC 2025, imec has announced a new milestone: using the same Si interposer platform, it has demonstrated a record-low insertion loss of just 0.73dB/mm at frequencies up to 325GHz.
“What sets our approach apart is the ability to mix and match digital, RF-to-sub-THz CMOS technology nodes with a wide variety of III/V chiplets – not limited to InP, but also including SiGe, GaAs, and others,” explained Xiao Sun, principal member of technical staff at imec.
The platform’s digital interconnects benefit from Cu damascene back-end-of-line (BEOL) processing, while mmWave signal paths employ transmission lines on a low-loss RF polymer layer. Additionally, high-quality passive components are integrated directly onto the RF silicon interposer, reducing the active chip area, lowering costs, and ensuring compact, low-loss RF interconnects for improved performance.
Imec’s technology combines RF/microwave links (with 5µm line width and 5µm spacing), with high-density digital interconnects (with 1µm/1µm line/spacing), and a fine flip-chip pitch of 40µm – with efforts underway to scale down to 20µm. Together, these features enable high integration density and a compact footprint.
As a next step, Xiao Sun and her team are preparing to augment the platform with additional features including through-silicon vias, back-side redistribution layers, and MIMCAPs for supply decoupling.
In parallel, imec is preparing to open its RF interposer R&D platform to partners for early assessment, system validation, and prototyping – amongst others by making it accessible via NanoIC, imec’s sub-2nm pilot line as part of the EU Chips Act.
