Expected to start production in 2028, TSMC said that the development of the A14 was “progressing smoothly” with a yield performance that was ahead of schedule.
The A14 is expected to harness 2nd Gen gate-all-around (GAA) nanosheet transistors, that will be enhanced by TSMC’s NanoFlex Pro technology, and will provide greater performance, power efficiency and design flexibility, according to the company.
TSMC went on to claim that the A14 will offer up to a 15% speed improvement at the same power, or up to a 30% power reduction at the same speed, along with more than a 20% increase in logic density.
Other versions of the A14, including a high-performance variant (A14X) and a more cost-effective version (A14C) are expected to roll out around 2029.
TSMC is also advancing its Chip on Wafer on Substrate (CoWoS) technology to meet AI’s growing demand for logic and HBM.
The company used its Symposium to reveal that its ‘System on Wafer-X’ will be able to weave together at least 16 large computing chips, as well as memory chips and fast optical interconnections. It plans to build two new factories to carry out this work near its chip plants in Arizona, with plans for a total of six chip factories, two packaging factories, and a research and development centre at the site.
Chip integration is now a key battleground between TSMC and Intel and is a complex task that requires them to work closely with customers. Intel is set to announce several new manufacturing technologies.
TSMC’s ability to stitch together 16 computing chips is significant. At present Nvidia's flagship GPUs consist of just two large chips while its ‘Rubin Ultra’ GPUs, which are expected in 2027, will comprise of just four chips.
In terms of the competition between TSMC and Intel, it appears that technological differences are becoming less significant and that issues like customer service, pricing and how much wafer allocation can be obtained are now more influential in terms of how customers decide which chip manufacturer would be best.
