Libero v11.7 introduces an enhanced constraints flow aimed at simplifying the management of all constraints in a design. The solution is used to manage timing constraints, I/O attribute constraints, floor planning constraints and netlist attribute constraints to ensure they can be created, imported, edited and organised in a single view. Timing constraints for known hardware blocks and intellectual property (IP) elements are derived automatically.
The software release also features a redesigned ChipPlanner, a floor planning tool used to define and assign logic to regions within the FPGA. The ChipPlanner also includes interface updates and runtime enhancements, most notably on large and highly utilized designs.
For the SmartFusion2, IGLOO2, and RTG4 FPGAs, SmartDebug allows visibility into FPGA designs without the need to reinstrument and rebuild the design. In addition SmartDebug allows users to read and write to LSRAM, uSRAM and SerDes control registers.
The release of Libero SoC v11.7 also marks the production release of its Secured Production Programming Solution (SPPS) which is used to prevent overbuilding, cloning, reverse engineering, malware insertion and other security threats.
