The ZL40292 (85Ω termination) and ZL40293 (100Ω termination) have been specifically designed to meet the new DB2000Q specification while the ZL40294 (85Ω termination) and ZL40295 (100Ω termination) are designed to meet the DB2000QL industry standard. These new devices also meet PCIe Gen 1, 2, 3 and 4 specifications.
Each buffer is intended as a complement to chipsets where distributed clocks are required across several peripheral components, such as Central Processing Units (CPUs), Field Programmable Gate Arrays (FPGAs) and Physical layers (PHYs) in data centre servers and storage devices, along with many other PCIe applications.
The devices’ low additive jitter of approximately 20 femtoseconds (~20 fs) far exceeds the DB2000Q/QL specification of 80 femtoseconds (80 fs) and provides designers with large margins to meet tight timing budgets while achieving increasing data rates. These devices will minimise jitter when distributing clocks to up to 20 outputs, thereby maintaining the integrity and quality of the clock signal through the buffer.
The new buffers achieve low power dissipation and contribute significant savings to power budgets by using Low-Power High-Speed Current Steering Logic (LP-HCSL). Compared to standard HCSL, LP-HCSL consumes one third of the power, leading to a significant decrease in power consumption. This feature also gives customers the ability to drive longer traces on their board, improving signal routing while reducing components and board space. The ZL40292, for example, can eliminate up to 80 termination resistors (four per output) compared to traditional HCSL buffers
