TSMC unveils 16nm FinFET design flows
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Three new reference flows have been released by TSMC for 16nm FinFET SoC designs and 3d stacked ics.
Developed within the Open Innovation Platform (OIP) in collaboration with a number of leading eda vendors, the design flows include: a digital design flow for TSMC's 16FinFET process; a custom design flow for 16FinFET that offers transistor level design of analogue, digital, mixed signal, custom digital and memory; and a 3d ic flow for the design of vertically stacked structures and multi die assemblies.
"These reference flows give designers immediate access to TSMC's 16FinFET technology and pave the way to 3d ic Through-Transistor-Stacking (TTS) technology," said TSMC vp of R&D, Dr Cliff Hou.
"Delivering our most advanced silicon and manufacturing technologies as early and completely as possible to our customers is a major milestone for TSMC and its OIP design ecosystem partners."
The 16FinFET digital reference rlow uses the ARM Cortex-A15 multicore processor as a validation vehicle for certification. TSMC says it helps designers adopt the new technology by addressing FinFET structure related challenges of complex 3d resistance capacitance (RC) modelling and quantised device width.
In addition, the flow provides methodologies for boosting power, performance and area in 16nm, including low voltage operation analysis and high resistance layer routing optimisation for interconnect resistance minimisation.
