Synopsys gets OK for 16nm FinFET design flow

EDA software vendor Synopsys has announced that its Galaxy design flow has been certified by TSMC as suitable for designs aimed at its 16nm FinFET process.

The V1.0 certification covers both custom and cell based designs. The tools oriented towards cell based design include: Design Compiler for synthesis, IC Compiler for physical implementation, IC Validator for physical verification, StarRC for parasitic value extraction and PrimeTime for timing analysis. The custom design tools include HSpice circuit simulation, FastSpice, CustomSim and FineSim tools, static timing analysis with NanoTime and custom implementation with the Laker custom design and layout tool. Suk Lee, pictured, senior director of marketing for TSMC, said: "Given the complexity of dealing with 3D transistors, we started early and significantly broadened our collaboration with Synopsys to deliver on the promise of FinFET technology. "With the availability of V1.0 certified tools, all our customers can now realise the full potential of FinFET technology."