In fact, in the case of some designs, these power demands can account for 50% of the total device power budget. For battery powered applications with a constrained form factor, this is creating huge challenges for the design team to create a viable product.
In response to this sureCore has developed EverOn, an ultra-low power memory device.
“This ultra-low power memory device can make these product designs feasible as they need up to 50% less power than standard ‘off-the-shelf’ memories,” explained Paul Wells, CEO of sureCore, an embedded memory specialist. “The power penalty for extra features is now recognised by designers as a real limitation for next generation devices and, as a result, we are signing multiple licensing deals for smart watches, fitness trackers and earbuds. Our SRAM IP is silicon proven in ‘leading foundry’ processes enabling customers to minimise power demand increases and gain fast time to market.”
With low voltage design methodologies becoming more prevalent as a route to cutting operating power, this is being achieved by dynamically reducing operating voltages in line with the applications processing demands.
Standard logic cells can, with careful design, operate over a wide voltage range, often close to near threshold voltages. However, off-the-shelf SRAM IP can only operate around the process nominal voltage. Integration of the two on the same chip means having two different power rails with level shifting circuitry, which consumes a lot of power, to provide the higher voltage for the memory plus extra circuitry to handle signals crossing between voltage domains.
This adds to the complexity of the design and its verification as well as adding silicon real estate.
EverOn SRAM IP has been specially designed for these kinds of systems where the voltage is adjusted to save power with operation from the process nominal operating voltage all the way down to the bit cell retention voltage that effectively dictates the lowest possible operating voltage.
In a leading 40nm process technology, this means from 1.21V down to 0.6V without any additional circuitry or power rails. Hence the voltage of the chip can be dynamically adjusted up and down in tandem with the performance requirements for the operation in hand to save power as required. For example, this could be going from a high performance to a low performance mode or even a monitoring state awaiting a wake-up event. This makes the chip design much simpler. By contrast, adjusting the voltage in chips with traditional memory is far more complex as, while the logic part is easy to drop, the voltage to the memory needs to be maintained at the higher operational voltage.
Off-the-shelf SRAM IP has typically been optimised for either high density or high speed rather than power, and this creates challenges for integration in a variable voltage, power-optimised system. EverOn is able to achieve operating voltage flexibility by the use of sureCore’s patented SMART-Assist circuitry that is an integral part of the IP thereby conferring much-simplified integration and verification requirements. This methodology is an effective strategy for architects to deliver power savings of up to 50% compared to traditional approaches.
“Being able to easily and dynamically drop the voltage of a chip is key to saving power,” explained Tony Stansfield, sureCore’s CTO, “because power is proportional to the square of the voltage. For example, dropping from 0.9V to 0.6V roughly halves the power. In battery operated devices, low power is paramount so this amount of saving can be significant in designs that have a lot of memory. There is a constant drive to make these devices ‘smarter’ with more intelligence which means increasing amounts of memory that have to be very power designs to make the power budget and battery capacity calculations work. EverOn ultra-low power memory makes the next generation of intelligent, battery-powered devices possible.”