sureCore delivers ultra-low power register files

2 min read

sureCore, the embedded memory specialists, has unveiled the MiniMiser that reduces the power consumption of register files by over 50%.

Register files are small blocks of memory that typically interface directly to high performance logic to provide fast access to data needed for calculations. These are often located inside the related compute blocks to reduce wiring delays and ensure both power and performance targets can be met.

Their activity level directly matches that of the logic they are coupled to so, as a result, power requirements can contribute significantly to the overall power budget of the chip.

To address this sureCore has developed MiniMiser to cut register file power consumption in next generation, battery-powered devices where extending recharge cycle times is crucial.

Commenting Tony Stansfield, sureCore’s CTO, said “Standard off-the-shelf Register File IP is usually based on the foundry bit cell, and whilst this give optimal area utilisation, the power metrics are often poor – with the bit cell itself precluding a reduction in operating voltage to tune the logic for a range of performance goals.

"Designers are forced to implement multiple power islands – at least one for the logic and one for the memories. This introduces a level of physical design complexity plus the addition of level shifters as well as necessitating considerable care with the timing analysis strategy. Our register file architecture readily supports both a wide operating voltage range as well as the capability to deliver the high performance needed by AI applications.”

Stansfield added, “sureCore has considerable expertise in this space and we have worked with some of the world’s leading companies who are exploiting this capability to utilise various operating voltages to deliver the performance needed by the application in a given mode.”

sureCore first delivered an SRAM capable of similarly offering a wide operating voltage range over 4 years ago which developers have taken advantage of for identical reasons. In that case, the memory is based on the foundry bit cell with the company’s patented SMART-Assist technology ensuring the bit cell is always operated in the foundry recommended voltage window.

The MiniMiser architecture is based on a customised storage element and exploits sureCore’s SRAM power saving techniques to deliver significantly improved power characteristics even at nominal process voltages. The architecture lends itself to several optimisation criteria – multi-port and high-performance variants can be readily generated by the company’s powerful proprietary compiler technology. As MiniMiser is not based on the foundry bit cell then its yield characteristics, like the logic, follow the process d0 thereby easing DFT considerations.

Paul Wells, sureCore’s CEO, concluded, “MiniMiser gives developers a new way of optimising the power envelope for their design. Savings of over 50% can be delivered just by swapping in MiniMiser instances. By reviewing the application’s operational demands they can further enhance this by introducing multiple performance modes tied to various operating voltages thereby ensuring the SoC is tuned to application need without the usual design headaches mentioned above. As wearable devices have more and more AI built in to enrich the user experience and provide product differentiation, more memory will be needed to support the computing demands. Cutting their power use has become increasingly important in the quest to achieve a competitive power budget.”