RIOS Laboratory and Imagination look to grow RISC-V ecosystem

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Imagination has announced a complete course on RISC-V computer architecture for undergraduate teaching as part of its Imagination University Programme (IUP).

“RVfpga: Understanding Computer Architecture” includes a detailed set of teaching materials and practical exercises to help students understand the key elements of processor architecture, including IP cores, modifying a RISC-V core and their microarchitectures.

Professor David Patterson, who shares the ACM A.M. Turing Award with John Hennessy for contributions to RISC, says; “RISC-V is transforming processor design and software/hardware co-design. RISC-V is an open architecture, which enables open-source hardware implementations. This new option means that software development can occur alongside hardware development, accelerating the design path. The RVfpga course enhances the understanding of not only RISC-V processors but also the RISC-V ecosystem and RISC-V SoCs. This course provides a deep understanding of an industrial-strength processor architecture and system of increasing popularity, which will prove useful to students throughout their academic and industry careers.”

The course is created in association with academic partners Associate Professor Sarah Harris, co-author of the popular “Digital Design & Computer Architecture” textbook which has been published in more than five languages and is a cornerstone of courses in computer architecture, and Associate Professor Daniel Chaver.

The course includes an instructor’s guide, a student manual, 10 comprehensive Labs (hands-on experiments), test materials, sample exam questions, and all the associated IP and software.

To enable use in whole or in part, the source files of all the materials is provided. This flexible and open approach allows academic institutes to teach a fully featured course with the ability to augment or adapt as each teacher requires.

“RISC-V improves on previous processor generations in every conceivable way, from power consumption to performance and even increased security," said Professor Harris. "As another huge step forward in computer architecture it is important for students to understand RISC-V at a fundamental level.”

Key dates:

  • 3rd September 2020, 2.55pm PDT – Associate Professors Sarah Harris and Daniel Chaver will be giving a presentation about the course at the RISC-V Global Forum
  • 8th October 2020 – The IUP will be hosting a webinar on the course. To register use the link below.
  • November 2020 – Release of the complete course in English, to be followed by Chinese, Spanish and Japanese