OpenHW announces tape out of RISC-V-based CORE-V MCU Devkit

1 min read

OpenHW Group has unveiled a comprehensive Development Kit for an open-source RISC-V MCU.

Available for order the OpenHW CORE-V MCU DevKit includes an open-source printed circuit board (PCB) which integrates OpenHW’s CORE-V MCU and various peripherals, a software development kit (SDK) with a full-featured Eclipse-based integrated development environment (IDE), as well as connectivity to Amazon Web Services (AWS) via AWS IoT ExpressLink for secure and reliable connectivity between IoT devices and AWS cloud services.

The DevKit will enable software development for embedded, internet-of-things (IoT), and artificial intelligence (AI)-driven applications. The CORE-V MCU is based on the open-source CV32E40P embedded-class processor, a small, efficient, 32-bit, in-order open-source RISC-V core with a four-stage pipeline that implements the RV32IM[F]C RISC-V instruction extensions.

“This highly anticipated CORE-V MCU based on the revolutionary RISC-V architecture, has successfully taped-out and the DevKit is now available for ordering,” said Rick O’Connor, President and CEO, OpenHW Group. “The collaborative efforts of the open-source community have once again proven their ability to drive innovation and deliver essential building blocks for next-generation MCU designs.”

The DevKit’s SDK, developed by an OpenHW team, contains an IDE, Debugger, GCC compiler (supplied by Embecosm), FreeRTOS real-time OS, and demo software.

This project highlights the open-source collaborative development of industry-grade CORE-V processor IP with supporting hardware and software by a wide spectrum of members within the OpenHW community.

For example, the CORE-V MCU is manufactured by GlobalFoundries’ proprietary 22FDX process technology platform while the design and verification of the CV32E40P processor, the heart of the CORE-V MCU, involved key contributions from Imperas, Siemens EDA, SiLabs among others, building on the original design from ETH Zurich.

The CV32E40P core is based on the PULP (Parallel Ultra Low Power) Platform RI5CY core, originally developed at ETH Zurich’s Integrated Systems Laboratory (IIS) and the Energy-efficient Embedded Systems (EEES) group of the University of Bologna.