The expansion includes new innovations with EdgeLock secure enclave to enhance edge security and Energy Flex architecture to maximize energy efficiency.
"The next evolution of the edge will be driven by distributed intelligence across billions of devices, and that requires profound innovations in processing, energy efficiency, and security,” said Ron Martino, senior vice president and general manager, Edge Processing Business, NXP Semiconductors. “Our announcements mark an industry milestone in ultra-low power processing and trusted cloud-to-edge security.”
The EdgeLock secure enclave is a pre-configured security subsystem that simplifies implementation of complex security technologies and helps designers avoid costly errors. It enhances protection to the edge device by autonomous management of critical security functions, such as root of trust, run-time attestation, trust provisioning, secure boot, key management, and cryptographic services, while also simplifying the path to industry-standard security certifications.
The EdgeLock is able to intelligently track power transitions when end-user applications are running to help prevent new attack surfaces from emerging.
NXP said that the secure enclave will be a standard integrated feature across the i.MX 8ULP, i.MX 8ULP-CS with Azure Sphere, and i.MX 9 applications processors, providing developers with a wide range of compute scalability options to easily deploy security on thousands of edge applications.
Keeping an edge device secure long after initial deployment is a challenge so NXP has partnered with Microsoft to bring this capability to its customers with Azure Sphere chip-to-cloud security in the i.MX 8ULP-CS (cloud secured) applications processor family.
The i.MX 8ULP-CS with Azure Sphere incorporates Microsoft Pluton enabled on EdgeLock secure enclave as the secured root of trust built into the silicon itself, and as a key step toward enabling highly secured devices for a vast range of IoT and industrial applications.
In addition to the secured hardware, Azure Sphere includes the secured Azure Sphere OS, the cloud-based Azure Sphere Security Service, and ongoing OS updates and security improvements for over ten years. Azure Sphere chip-to-cloud security will be enabled on specific products within the i.MX 9 series, giving developers an even broader set of processor options to implement managed device security across their products.
“This collaboration is going to empower a whole new class of connected devices supported by ongoing security improvements. The i.MX 8ULP-CS with Microsoft Azure Sphere will provide security, productivity, and opportunity for partners,” said Dr. Galen Hunt, Distinguished Engineer and Managing Director, Microsoft Azure Sphere. “By combining the power and flexibility of the NXP i.MX family of chips with intelligent, responsive Azure Sphere security at scale, customers can transform products, services, and experiences with confidence, knowing that Microsoft has their back.”
The i.MX 8ULP and i.MX 8ULP-CS families implement NXP's Energy Flex architecture to deliver as much as a 75% improved energy efficiency than its predecessor by combining heterogeneous domain processing, design techniques and 28nm FD-SOI process technology. Embedded in these processors is a programmable power management subsystem that can govern more than 20 different power mode configurations to deliver exceptional energy efficiency – from full power to as low as 30 microwatts.
Using this range of flexible configurations, OEMs and developers can customise application-specific power profiles to maximize energy efficiency.
NXP’s i.MX 9 series debuts a new generation of scalable, high-performance processors that bring together higher performance applications cores, an independent MCU-like real-time domain, Energy Flex architecture, state-of-the art security with EdgeLock secure enclave, and dedicated multi-sensory data processing engines (graphics, image, display, audio and voice).
The i.MX 9 series integrates hardware neural processing units across the entire series for acceleration of machine learning applications. It also marks NXP’s first implementation of the Arm Ethos U-65 microNPU, which makes possible building low cost, energy-efficient edge machine learning (ML).
The first families in this series will be built in 16/12nm FinFET class of process technology with specific low power optimisation.
