Mobiveil and Avery Design to accelerate verification of NVMe 2.0-enabled SSD development

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Mobiveil and Avery Design Systems have expanded their ongoing partnership to help customers accelerate NVMe-based SSD design and verification.

The complementary intellectual property/verification IP (IP/VIP) solution combines Mobiveil’s design IP for NVM Express, DDR4 and LDPC IP with Avery’s verification IP for NVMe, DDR4 and ONFI and NVMe virtual platform solutions. The two companies are also collaborating on SSD emulation platforms.

NVMe technology is an interface for SSDs and offers the potential for tremendous market growth worldwide. NVMe architecture is designed for future SSD development and form factors as the semiconductor industry enters a new era in hyperscale and enterprise computing that is driving digital transformation.

“As the NVMe standard continues to evolve to meet new and changing requirements, it is important that product developers have access to design and verification solutions that allow them to take full advantage of the latest features and are complaint with the standard. Our NVMe VIP and virtual platform solutions provide pre-silicon SSD SoC hardware and system-level verification solutions for the latest NVMe 2.0 designs. Our partnership with Mobiveil means that together we can deliver best-in-class IP design and verification solutions to our customers including simulation, FPGA emulation, and virtual system platforms,” explained Chris Browy, vice president of sales and marketing at Avery.

Mobiveil’s UNEX NVM Express Controller IP and Avery NVMe-Xactor supports the latest NVMe 2.0 specifications and, in addition, Mobiveil’s ONFI/Toggle IP (EFC) supports the latest ONFI 5.0 specifications. Both IP are fully verified using Avery Design’s NVMe/PCIe and ONFI VIP solutions.

Avery offers a complementary set of VIP for NVMe to ensure comprehensive verification and protocol and timing compliance. It includes a complete set of models, protocol checkers and compliance test suites in 100% native SystemVerilog and UVM. The support for virtual platform co-simulation enables full system-level verification including running UNH-IOL INTERACT and other Linux-based performance analysis applications on pre-silicon NVMe SoC designs.

“By providing pre-verified and interoperated SSD Design IP and Verification IP, both companies allow SoC design and verification teams to focus on their primary goal of full chip design and verification, thus significantly reducing their time to market,” said Ravi Thummarukudy, Mobiveil’s CEO. “By leveraging the intellectual property provided by these companies with specification-compliant solutions, designers can be assured of first-time success for their SoC designs”.