MIPS enters RISC-V market with eVpcore product line-up

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MIPS, a developer of RISC processor IP, is entering into the RISC-V market and has offered previews of its first products in its eVocore product line-up.

The eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard.

eVocore products build on MIPS’ leadership in high-performance, real-time compute applications such as networking, datacentre, and automotive. According to Semico Research, the CAGR for SoCs shipping with RISC-V CPU cores between 2020 and 2027 is 73.6%, with the automotive segment projected to achieve a 69.9% CAGR during that time.

 “We will see continued adoption of RISC-V in areas such as automotive as companies see the possibilities for differentiation that an open software development environment can provide,” said Rich Wawrzyniak, principal ASIC and SoC analyst, Semico Research. “With MIPS’ long history providing RISC architectures and cores and its strong footprint in automotive, networking and other high-performance applications, the company’s move to RISC-V makes sense for the next stage of its growth.”

“With this transition to RISC-V, MIPS is targeting the high-performance segment of the processor market,” explained MIPS CEO Desi Banatao. “By leveraging our differentiation in real-time features, hardware virtualization, functional safety and security technologies, we can offer compelling products for automotive, edge compute, networking and switching, and large-scale computing systems.”

Highly scalable and configurable the RISC-V compatible eVocore IP cores are designed to provide a high level of scalability and will enable customers to blend coherent clusters of multi-threaded, multi-core CPUs in combinations to meet their exact power and performance requirements.

The cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices.

Because the RISC-V ISA enables the addition of custom features in the form of user defined instructions (UDIs), MIPS can uniquely deliver proven and powerful features which are required in many high-end applications, while also being fully compatible with off-the-shelf RISC-V development tools and software libraries.

Both of the new eVocore IP cores provide support for privileged hardware virtualization, user defined custom extensions, multi-threading, hybrid debug, and functional safety and make them well suited for compute-intensive tasks across a broad range of markets and applications.

The eVocore P8700 multiprocessing system combines a deep pipeline with multi-issue Out-of-Order (OOO) execution and multi-threading to deliver improved computational throughput. It has single-threaded performance greater than what is currently available in other RISC-V CPU IP offerings, and it can scale up to 64 clusters, 512 cores and 1,024 harts/threads. The eVocore P8700 will be available in Q4 2022.

The eVocore I8500 is an in-order multiprocessing system delivering best in class power efficiency for use in SoC applications. Each core combines multi-threading and an efficient triple-issue pipeline to deliver outstanding computational throughput.