Microchip provides new design resources and tools for PolarFire FPGAs and SoCs

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Microchip has announced a number of new development resources and design services to support designers switching to PolarFire FPGAs and SoCs.

These new resources include the industry’s first mid-range industrial edge stack, ready-to-customise cryptography and boot libraries of soft intellectual property (IP) and new tools to convert existing FPGA designs to PolarFire devices.

These additions expand Microchip’s suite of tools and services supporting the PolarFire family of devices – which includes the only RISC-V SoC FPGA shipping in volume production. 

“The intelligent edge demands the very best in power efficiency, security, safety and reliability,” said Shakeel Peera, vice president of strategy for Microchip FPGA. “Our new mid-range industrial edge stack and related tools offer more than just automation IP and enable secure edge compute, analytics, machine learning and high-availability data interconnects for Industrial IoT end points.” 

“Customers are switching to PolarFire FPGAs and SoCs because they can create products that weren’t possible before, establish clear product differentiation and accelerate their time to innovation,” said Bruce Weyer, corporate vice president of Microchip FPGA. “Our mid-range technology leadership and RISC-V-based compute solutions offer system architects design flexibility and efficiency.”

To back its FPGA-based embedded processor portfolio, Microchip offers broad RISC-V development support with more than 60 companies now in its Mi-V ecosystem.

The seven new resources and conversion tools offer a range of benefits at every stage of design and development, making it much easier to switch to PolarFire FPGAs and SoCs.

They include: 

  • A comprehensive industrial edge stack for Open Platform Communications/Unified Architecture (OPC/UA)-based IIOT applications.
  • Cryptography and boot soft IP libraries that can be fully customised.
  • Direct conversion scripts to move quickly from other vendors’ FPGAs, including step-by-step tutorials to switch from these alternative FPGA families.
  • A high-performance AI/ML development flow that lets algorithm creators build their own mid-range FPGAs. This solution features SmartHLS compiler software, the VectorBlox accelerator software development kit (SDK) and neural-network IP.
  • A new PolarFire SoC development kit.
  • A tutorial, presentation and resource guide on how to design cool-temperature edge nodes.
  • Microchip is also making available a new power-consumption tutorial and a tool to evaluate any design’s power efficiency and thermal management within vendor-provided estimators.

All these additional resources join a comprehensive suite of FPGA design services including consulting, use-case modelling and test benches to programming, validation and prototype builds, design optimisation and fitting, current and custom IP and firmware development.

Microchip FPGA’s Libero SoC Design Suite integrates an IP library (available in evaluation, no-charge and RTL versions), and the VectorBlox Accelerator supports the most common frameworks.

Both are available to license, including no-charge versions. The OPC/UA industrial edge stack is expected to be available this quarter.