Microchip releases C++ synthesis suite for PolarFire FPGA algorithm development

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Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) code.

The announcement comes in response to the growing need for designers to combine performance with low power consumption in edge compute applications and which has driven demand for Field Programmable Gate Arrays (FPGAs) to be used as power-efficient accelerators. However, a large majority of edge compute, computer vision and industrial control algorithms are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware.

“SmartHLS enhances our Libero SoC design tool suite and makes the vast benefits of our mid-range PolarFire and PolarFire SoC platforms accessible to a diverse community of algorithm developers without them having to become FPGA hardware experts,” said Bruce Weyer, vice president of Microchip’s FPGA business unit. “Together with our VectorBlox Neural Network Software Development Kit these tools will improve designers’ productivity in creating cutting-edge solutions using C/C++ based algorithms for applications such as embedded vision, machine learning, motor control and industrial automation using FPGA-based hardware accelerators.”

Based on the open-source Eclipse integrated development environment, the SmartHLS design suite uses C++ software code to generate an HDL IP component for integration into Microchip’s Libero SmartDesign projects. This enables engineers to describe hardware behavior at a higher level of abstraction than is possible with traditional FPGA RTL tools.

According to Microchip it improves productivity while reducing development time through a multi-threading Application Programming Interface (API) that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism as compared to other HLS offerings.

The SmartHLS tool requires up to 10 times fewer lines of code than an equivalent RTL design, with the resultant code being easier to read, understand, test, debug and verify. The tool also simplifies exploration of hardware microarchitecture design trade-offs and enables a developer’s pre-existing C++ software implementations to now be used with PolarFire FPGAs and FPGA SoCs.