Mentor pushes for graph based test standardisation

Mentor Graphics has proposed that a new Accellera standards committee be formed to investigate the standardisation of graph based test.

John Lenyo, pictured, general manager of Mentor's Design Verification Technology Division, said: "Based on customer feedback, we're moving forward to recommend and facilitate a standards effort that brings significant benefits to a large number of users and which opens the door to technology innovation."

Graph based test is said to have three main benefits: it reduces the time spent writing and debugging tests by at least 50%; it supports multiple design languages and multiple verification environments; and its abstract nature allows the test specification to be executed in different ways, according to verification requirements. However, Mentor points out that graph based test is not a new development, being based on the standard Backus-Naur Form pioneered by IBM and used by a range of companies to automate compiler testing. Looking to kick start the process, Mentor is donating its graph based test specification format. This has been augmented to support VLSI design verification across all standard environments and languages, including Verilog, VHDL, SystemVerilog, e, SystemC, C/C++ and assembly code.