HyperLynx now offers complete high speed PCB support

2 mins read

Mentor Graphics has unveiled the latest version of HyperLynx which integrates signal and power integrity analysis, 3D-electromagnetic solving, and fast rule checking into a single unified environment. For the first time it is able to offer designers a complete set of analysis technology sufficient for designing any type of high-speed digital printed circuit board (PCB).

HyperLynx supports a wide range of underlying simulation engines and has a graphical user interface (GUI) that supports both quick/interactive and exhaustive batch-mode analysis.

High-speed PCBs can vary significantly in terms of size, layer count, routing density, signaling speed, the types of silicon used, and power-delivery, as a result most tool sets typically require switching applications and user interfaces for different types of analysis.

The HyperLynx tool offers 2D/3D signal and power integrity analysis in a single application, with one GUI. Users can now simulate a critical SERDES channel and then switch to analysis of a large power net’s decoupling by simply selecting from a single new menu.

HyperLynx is now able to produce highly accurate simulations by combining a super-fast geometry extraction engine and advanced materials modeling (for wideband dielectrics, copper roughness, etc.).

“This version of HyperLynx is the culmination of intensive investment by Mentor in its high-speed tools,” explained A.J. Incorvaia, vice president and general manager of Mentor Graphics Systems Design Division. “HyperLynx has long been a widely used high-speed tool in the industry; now it’s become the most powerful and best integrated.”

SERDES technology adoption has greatly increased the frequencies used in digital signaling— even a “mainstream” protocol like PCIe Gen3 runs at 8 Gb/s – and this version of HyperLynx provides advanced electromagnetic solvers, including full-wave 3D, enabling users to keep pace with increasingly fast SERDES technologies. The 3D engine is deeply integrated which ensures that signal and power structure geometries are passed; electromagnetic (EM) ports are formed; simulations are run; and S-parameter results are incorporated into time-domain simulations automatically.

This version of HyperLynx has added multiple engines to enable a full set of power-integrity features, all of which are available side-by-side in the same application as signal-integrity capabilities. The second, more-advanced 2.5D solver is capable of pure power and mixed signal-and-power modeling, which can then be used to add accuracy to SI simulations when simultaneous-switching-noise (SSN) complications are suspected.

According to Mentor simulating every detail of a PCB’s signal routing and power delivery can be overwhelming for design engineers, but by tuning raw simulation capabilities to the specific requirements of standard interfaces and protocols (like DDRx memory and 100-Gb/s Ethernet SERDES) HyperLynx can provide streamlined, summary pass/fail judgment on entire interfaces.

The HyperLynx wizard for DDRx memory interfaces pioneered easy setup, automated whole-bus simulation, and consolidated results reporting – and has now been extended to DDR4 and LPDDR4 interfaces. HTML-based reporting allows creation of design documentation and internal Web-based “publication” of results.

In the SERDES arena, protocols that support Channel Operating Margin (COM) allow checking the quality of links based on a specific, complex set of simulation steps for a single pass/fail number per-channel. This new tool offers the industry’s first robust commercial implementation of COM for 100GbE signaling, with simulation details fully automated.

This HyperLynx version is also capable of handling very large layouts (including extra-deep stack-ups, huge net counts, and entire multi-board systems); multi-processor and other simulation-engine performance enhancements; and caching and re-use of extracted models.