The VP460 Direct RF Processing System is aligned with the SOSA standard to deliver cost-effective interoperability, which is required by the US military. The 6U VPX platform complements the previously announced VP430 3U VPX Direct RF Processing System.
Designed to enable development of advanced, next generation multi-channel electronic warfare systems in application areas such as MIMO, beamforming, sensor processing, radar, SDR and signals intelligence, the VP460 provides both a high level of performance and channel density.
It features 16 integrated analogue-to-digital converters at 2GSPS, and 16 digital-to-analogue converters at 6.4 GSPS. Also included are a user-programmable FPGA fabric and multi-core Zynq ARM processing subsystem. The HBM VU37P device features the speed and capabilities of an UltraScale+ FPGA together with integrated DRAM in the FPGA package, and is capable of up to 460GB/s on-chip data transfer rates.
By reducing RF signal chain complexity and leveraging heterogeneous processing capabilities, the VP460 has been designed to allow input/output channel density to be maximized and data offloaded more efficiently - without sacrificing onboard signal processing capabilities.
“Today’s electronic battlefield is seeing the accelerated growth of smart sensor systems – and is demanding more channels, more bandwidth, and as a result, more data processing capabilities,” said Peter Thompson, Vice President, Product Management at Abaco. “The VP460 is a revolution in COTS RF and FPGA processing, perfectly balancing the need for high performance FPGA processing, the ease of a hardened embedded processor and the ultra-low latency of integrated analog interfaces.
“With its ability to synchronize all 16 channels, as well as multiple boards for even larger system applications, the VP460 is one of the densest 6U VPX analog FPGA carrier boards available,”
Thompson continued. “In previous generations of technology, this combination would have taken four times as many boards. It can make a significant contribution to minimizing SWaP – which is vital in the increasingly constrained environments in which today’s systems are being deployed.”
With 16 ADCs sampling at rates up to 2GSPS with two bytes per sample, even the modern PCIe Gen3 high speed data connection is too slow for a direct transfer. To overcome this challenge, the VP460 includes – in addition to the PCIe Gen3 data plane - up to 64 high speed serial lanes to the Xilinx Virtex Ultrascale+ HBM device, supporting protocols such as PCIe Gen3, 10/40G Ethernet, Aurora etc.
The Xilinx RFSoC is being described as a revolutionary step in integration technology bringing a combination of Field Programmable Gate Array (FPGA) processing capability, a multi-processor embedded ARM Cortex-A53 Application processing unit (APU), and an ARM real time processing unit (RPU).
Additionally, the Zynq Ultrascale+ architecture integrates all this with features to enable high security IP protection.
