Cadence will be providing DDR4 Design IP (DIP) and Verification IP (VIP) support for Everspin’s 1 Gb STT-MRAM memory.
Cadence and Everspin have collaborated before on multiple projects, and Cadence has supported Everspin’s STT-MRAM products since 2012. With Cadence controller IP and VIP solutions, Everspin customers will be able to request MRAM-enabled IP and VIP for their Custom ASIC solutions. Everspin’s 1 Gb STT-MRAM product family includes both 8-bit and 16-bit DDR4 compatible (ST-DDR4) interface versions of the device and are available in a JEDEC-compliant BGA package.
“Our customers are inquiring about DIP and VIP support, so they can create new ASIC solutions which will support Everspin STT-MRAM,” said Everspin’s Vice President of Marketing Rizwan Ahmed. “Everspin’s growing ecosystem is now supported by Cadence controller IP and VIP solutions, which are used broadly in storage systems.”
Everspin’s STT-MRAM 1 Gb part offers more effective management of I/O streams, creating a greater level of latency determinism and allowing storage OEMs to significantly improve quality of service of their products. Customers requiring DIP and VIP support to enable Everspin’s 1 Gb STT-MRAM can now work with Cadence to achieve it.
“The compatibility of Cadence DIP and VIP with Everspin’s STT-MRAM will provide systems developers the ability to implement a high-speed, persistent memory host controller and PHY in advanced SoCs,” explained David Peña, product management director, VIP at Cadence. “We are pleased to be working with Everspin to bring advanced persistent memory capability to modern data center storage and computing applications.”