The three designs have been optimised for the company's Trion family of FPGAs and provide a range of compute and I/O capabilities in devices from the T8 to the T120.
“RISC-V is a versatile and efficient embedded compute solution,” said Mark Oliver, senior director of marketing at Efinix. “Based on the efficient VexRiscv design, our Trion family of SoCs delivers pre-optimised RISC-V cores across the entire Trion FPGA product line from the cost optimised T8 right up to the T120. Users can now easily create and deploy entire SoCs including embedded compute, I/O and custom functionality.”
For ease of use, the SoCs are preconfigured with a RISC-V core, memory, a range of I/O and have interfaces for embedding user functions. In this way, designers can easily create entire systems that include embedded compute and user defined accelerators within the same FPGA.
“Since winning the RISC-V Soft CPU contest in 2018 and the Linux support addition, the VexRiscv core has been rising in popularity inside the open source community,” said Charles Papon, the designer of VexRiscv. “Optimising the core into pre-defined configurations on the Trion family of FPGAs will give a much larger number of designers a turnkey and cost-effective way to access the power of the core in a broad variety of system designs.”
Efinix RISC-V SoCs come with a complete set of tools for compiling and debugging application code on the RISC-V core along with example applications and tutorials. They are compatible with the entire suite of Efinix development and evaluation boards and can be instantiated using the standard Efinity tool flow.
