Edge learning breakthrough

1 min read

CEA-Leti scientists have demonstrated a machine-learning technique that exploits the “non-ideal” traits of resistive-RAM (RRAM) devices, and in the process overcoming barriers to developing RRAM-based edge-learning systems.

In a paper published in the January issue of Nature Electronics, the research team demonstrated how RRAM, or memristor, technology can be used to create intelligent systems that learn locally at the edge, independent of the cloud.

The learning algorithms used in current RRAM-based edge approaches cannot be reconciled with device programming randomness, or variability, as well as other intrinsic non-idealities of the technology.

To get around this, the team developed a method that actively exploits that memristor randomness, implementing a Markov Chain Monte Carlo (MCMC) sampling learning algorithm in a fabricated chip that acts as a Bayesian machine-learning model.

While machine learning provides the enabling models and algorithms for edge-learning systems, increased attention concerning how these algorithms map onto hardware is required in order to be able to bring machine learning to the edge. Machine-learning models are normally trained using general purpose hardware based on a von Neumann architecture, which is unsuited for edge learning because of the energy required to continuously move information between separated processing and memory centres on-chip.

The microelectronics industry is currently focused on using RRAM as non-volatile analogue devices in hardware-based artificial neural networks that can allow computation to be carried out in-memory, drastically reducing energy requirements. RRAM has been applied to in-memory implementations of backpropagation algorithms in order to implement in-situ learning on edge systems. However, because backpropogation requires high-precision memory elements, previous work has largely focused on how RRAM randomness can be mitigated.

The CEA-Leti team used an approach that leveraged this randomness, allowing in-situ learning to be realised in a highly efficient fashion through the application of nanosecond voltage pulses to nanoscale memory devices resulting in a very low-energy solution.

According to the team, relative to a CMOS implementation of its algorithm, this approach requires five orders of magnitude less energy.