The part, which is intended to compete with Cortex-M0 based MCUs, will run from a 1.2V supply and be supplied in a 32pin QFN. It will have 8k of SRAM and will be capable of running at up to 160MHz. Other features include two PLLs, two 10bit A/D converter channels, two 12bit D/A channels and 16 GPIO pins. On chip connection is handled – in part, according to the developers – using the AMBA bus.
Despite the use of an open source CPU and peripherals, the team is experiencing issues in integrating memory into the device. According to the crowdfunding page ‘integration of non-volatile memory on regular CMOS technology is a challenge, since the IP is controlled by only a few companies. Similarly, an IP license for NVRAM for pure CMOS has been difficult to find’.
However, the team says it has designed its own NVRAM and aims to test this on a TSMC multiproject wafer run scheduled for March 2017. If all goes to plan, the team hopes to have devices available in April 2018.
