This collaboration encompasses support for advanced memory interfaces including DDR4, DDR5, GDDR6, LPDDR4X and LPDDR5, as well as chiplet-based PHY IP and Cadence’s flagship 16G multi-protocol SerDes. The first product on the GF 12LP platform is the Cadence 16G Multi-Link and Multi-Protocol PHY, which is based on a high-performance multi-protocol architecture already well-proven in high volume production.
“GF is working closely with Cadence to enable high-performance SerDes and advanced memory interfaces to support our customers building advanced SoCs for high-performance computing, aerospace and defence applications, cloud/data centre servers, AI accelerators, and wired and wireless networking applications, as well as designers and customers leveraging die-to-die connectivity and pursuing chiplet architectures,” said Mark Ireland, vice president of ecosystem and design solutions at GF.
According to Ireland this combination of GF'S 12LP platform, specialised 12LP+ FinFET solution offerings, and Cadence design IP will enable customers to enjoy faster and more efficient development and certification of their complex SoCs.
GF’s most advanced FinFET solution, 12LP+ builds upon GF’s14nm/12LP platform, of which GF has shipped more than one million wafers.
“Cadence is making significant investments in enabling advanced IP. Together with GF, we are delivering mature, silicon-proven high-performance IP solutions that meet the needs of market-leading industrial and aerospace and defence companies,” added Rishi Chugh, vice president of product marketing, IP Group at Cadence. “Our expanding IP portfolio on the GF 12LP/LP+ process node unlocks a new set of customers for Cadence, allowing us to help accelerate development and time to market for their next-generation SoCs.”
