The flow, which incorporates leading implementation and signoff technology for ultra-low power designs, will enable customers to achieve a much faster path to tape-out.
The Cadence digital full flow that has been optimized for use on UMC’s 22ULP/ULL process technologies includes the Innovus Implementation System, Genus Synthesis Solution, Liberate Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Litho Physical Analyzer and Physical Verification System.
According to Cadence, the implementation and optimisation engines are fully integrated from RTL to GDSII, enabling users to achieve power, performance and area (PPA) goals and reduce time to market, while Cadence is able to offer the only digital flow with fully integrated place-and-route, timing signoff, physical verification and IR drop/power signoff capabilities, which provide unparalleled last-mile design closure with the fewest iterations.
“Our 22ULP/ULL platform is ideal for a wide variety of semiconductor applications, including power- or leakage-sensitive consumer chips and wearable products that require longer battery life,” said Y.H. Chen, director of the IP Development and Design Support Division at UMC. “By collaborating with Cadence, we’re providing access to our latest process technologies and Cadence’s robust digital full flow, which enables our customers to meet stringent design requirements and achieve design and productivity goals.”
Commenting Kam Kittrell, senior product management group director in the Digital & Signoff Group at Cadence said,“This certification allows UMC customers to leverage the most advanced low-power tool feature sets for synthesis, place-and-route, and signoff, enabling customers to design innovative applications with confidence.”
