Arteris unveils FlexNoC 5 physically aware Network-on-Chip IP

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Arteris, a provider of system IP which accelerates system-on-chip (SoC) creation, has announced the launch of the FlexNoC 5 physically aware network-on-chip (NoC) interconnect IP.

FlexNoC 5 will enable SoC architecture teams, logic designers and integrators to incorporate physical constraint management across power, performance and area (PPA) to deliver a physically aware IP connecting the SoC.

This technology is said to enable 5X faster physical convergence over manual refinements with fewer iterations from the layout team for automotive, communications, consumer electronics, enterprise computing, and industrial applications.

Manual workflows typically include numerous iterations of pipeline insertions, effort-intensive creation of constraints for physical placement of units, and lengthy NoC placement plus route iterations to converge on the SoC PPA targets. By contrast, FlexNoC 5 physical awareness eliminates these iterations and shortens the duration of various manual steps, speeding up the physical convergence of the back-end physical design time and effort.

The resulting physically optimised NoC IP instance is then ready for output to physical synthesis and place and route for implementation.

“Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect,” said Graham Curren, CEO of Sondrel. “Physical constraints have always been an important issue and are even more important below 16nm geometries. The latest FlexNoC 5 with its physical awareness technology, enables our RTL teams to verify that architectures meet physical constraints and provide a better starting point for our place and route team. We look forward to our continued cooperation with Arteris.”

In addition, FlexNoC 5 expands support for Arm AMBA 5 protocols and IEEE 1685 IP-XACT, including a connectivity flow with Arteris Magillem for NoC integration with other SoC IP blocks. FlexNoC 5 also supports the production-proven Arteris resilience option for automotive functional safety qualification and data centre reliability, the advanced memory option for optimising memory traffic, and the Arteris option for very large designs.

“Without physical awareness, it is quite possible to develop SoC architectures that are difficult or even impossible to place and route resulting in multiple turns, overall project delay risks, and additional project costs, particularly for geometries of 16nm and below,” said K. Charles Janac, president and CEO of Arteris. “With FlexNoC 5, we consider physical effects early in the process, delivering physically aware NoC IP which helps customers meet PPA goals and execute SoC projects on schedule and budget.”