The UHT-SCALER core is a video processing block used to resize (scale) input colour images of one size to output colour images of a different size. Output image can be smaller or larger than the original image, depending on the programmed scaling ratio.
The core can support scaling of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) video streams, in 8 up to 16 bits sample depth and has been found to provide excellent visual results by using bilinear, bicubic, lanczos or expfilter scaling algorithms.
The implementation is a fully accelerated, standalone and robust solution in a single IP instance, saving on ASIC or FPGA silicon area and power. The core does not need an external memory device for its implementation.
The UHT-SCALER IP is very easy-to-use and integrate in a system. It is self-contained, CPU-less, complete H/W implementation and is available either in RTL source code, or as pre-synthesised Netlist for all major FPGA vendor devices.
