Aldec: Verification tool takes fpga/asic debugging to next level

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Aldec has launched the latest version of its Riviera-Pro high performance, mixed signal language verification tool, which it claims takes fpga and asic debugging to the next level.

According to the electronic design verification specialist, the Riviera-PRO release version 2012.02 supports a number of advanced verification methodologies designed to benefit designers of complex fpgas and those migrating to asic. New features in version 2012.02 include support for the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. Aldec states that this last aspect also makes Riviera-PRO an ideal platform for working with the Open Source VHDL Verification Methodology. The new version also makes it possible to log class objects and display them in Riviera-PRO's Waveform Viewer and enables analysis of dynamic objects over time, organically combined with the objects of any other data type. It is also possible to log Information, warning and error messages; generated during simulation runtime in conjunction with appropriate markers displayed directly in the Waveform. Riviera-PRO release version 2012.02 also delivers enhancements to the tool's HDL Editor and Waveform Viewer.