Aldec adds UVM Generator to Riviera-PRO

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Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO.

The addition is intended to greatly boost the productivity of Riviera-PRO users taking advantage of the benefits of the Universal Verification Methodology, which contains guidance on the creation and reuse of verification testbenches.

Riviera-PRO’s new function automatically creates the UVM testbench (in SystemVerilog, the language that underpins the methodology) for any given design under test (DUT) written in VHDL or Verilog. It also creates a framework of the UVM code; one that contains comments indicating places that must be manually populated with design-specific code.

Along with SystemVerilog source files, the UVM Generator automatically creates the TCL macros for controlling the simulation process. The user can choose a DUT from a library or start a new design from scratch.

The UVM-generated code can also be displayed in Riviera-PRO’s UVM Graph Window, an existing and popular feature with users, for better visualization of the hierarchical UVM components, properties, connections, and dataflow - all of which greatly aid debugging.

Aldec has also updated the Open-Source VHDL Verification Methodology (OSVVM, a methodology the company played a significant role in creating) library to version 2021.06 within Riviera-PRO. In addition, the tool’s Universal VHDL Verification Methodology (UVVM) utility (uvvm_util) and VHDL Verification Component Framework (uvvm_vvc_framework) libraries have been updated to version v2021.05.26.