This solution enables an ultra-low-power sleep mode for a new generation of system-on-chips (SoCs).
Agile Analog provided XMOS, a fabless semiconductor company, with a comprehensive range of analogue IP blocks integrated into a single macro, incorporating the XMOS digital control system to form a complete always-on subsystem.
Agile Analog’s ultra-low-power IP included its configurable bandgap reference (agileREF), power-on-reset (agilePOR), oscillator (agileRCOSC), comparator (agileCMP), and capless LDO (agileLDO) IPs.
Commenting Barry Paterson, CEO at Agile Analog, said that the company was pleased to have successfully delivered its always-on IP subsystem for XMOS. “This project showcases the power of our Composa technology and our commitment to close collaboration with our customers. We are pleased to pave the way for further innovation in the development of next generation SoCs with ultra-low-power capabilities.”
Agile Analog’s Composa technology automatically generates analogue IP for any foundry and on any process. Each of these IPs can be configured to fit the customer’s exact requirements, allowing for optimal power and performance. The IP can also be delivered digitally wrapped to ease the integration process.
Over the last decade demand for always-on IP has rapidly increased, driven by the surge in smart wearable devices and remote monitoring systems. These rely on the ability to remain in a low-power state for extended battery life while maintaining the capability to wake up quickly to perform essential functions.
According to Chris Morrison, Director of Product Marketing at Agile Analog, “Our always-on IP subsystem includes all of the analogue circuitry required to minimise quiescent current in always-on applications. This is crucial for the energy efficient, responsive SoCs that are needed for the next wave of smart devices.”