Crystal maze

5 mins read

Subtle changes to crystal lattice and interface structures are bringing ferroelectric and possibly other low-power memories back from obscurity.

Every memory technology has its drawbacks. But if you compare the wish list to what it can handle in principle, ferroelectric memory (FeRAM) has to be close to the top of the pile. Like phase-change memories, that got their start more than a decade later, FeRAM has faced problems that for years effectively limited the technology to niche markets over the 70 years since its first appearance in the master’s thesis of MIT student Dudley Allen Buck, who also invented content-addressable memories and e-beam writers for custom PCBs.

As a memory technology that takes far less power to write values to non-volatile storage than flash, FeRAM has clear advantages in utility meters, where the available power is highly limited. Unlike flash, which calls for charge carriers to tunnel through a barrier, with the help of a relatively high charge, FeRAM just needs an asymmetric ion in a crystal to flip from one position to another. This seemingly minor change is enough to change the polarity of the cell in a detectable manner.

Unfortunately for first-generation commercial FeRAMs, the materials such as lead-zirconium titanate (PZT) employed to make that polarity flip happen were not all that compatible with fab processes.

A major stumbling block lay in the need for platinum electrodes. The noble metal’s lack of reactivity poses a major challenge for processes that largely depend on the ability to inject metals and dopants using gaseous carriers and then etch away the unwanted parts. For years, FeRAMs languished in the kilobyte range, though Texas Instruments found a way to improve yields to where useful memories could be integrated into microcontrollers. 

Potential breakthrough

A potential breakthrough for FeRAMs came in the mid-2000s thanks to the quest to find viable dielectrics that could replace silicon dioxide in the transistor gate stack. Hafnium dioxide did not just have a suitably high dielectric constant to allow the gate dielectric to be thinned to sub-nanometre depths. Engineers at memory maker Qimonda discovered that the hafnium ions showed ferroelectric behavior under certain conditions.

Because hafnium dioxide, along with its zirconium-doped relative HZO, can form directly onto silicon transistors without the need for exotic metal electrodes, this discovery provided a new lease of life for FeRAM.

Traditional PZT-based FRAMs needed to combine a silicon transistor paired with a ferroelectric capacitor, which also called for a destructive read process as the operation reset the charge in the capacitor. The work on hafnium-based materials has opened up the possibility of creating a memory cell directly on the gate of a CMOS transistor to form a FeFET. This should result in a smaller, denser memory cell. The material may also find use in tunnel junctions analogous to those used in magnetic memories and possibly far denser memories. The tunnel junctions would let manufacturers build 3D crossbar memories over logic. These structures high up in the metal stack may open up the possibility of using ferroelectric materials other than hafnium oxides that are less able to withstand the high temperatures of transistor formation.

Next generation problems

There is one problem with this new generation. Hafnium dioxide rarely demonstrates ferroelectric properties naturally. Ferroelectricity in the dielectric depends heavily on the conditions used not just to deposit it but to anneal it: the heat-driven process that repairs defects in the crystal lattice after deposition. Only one phase of the three into which hafnium dioxide naturally crystallises delivers a structure that makes it possible to polarise the ions and deliver the required ferroelectricity.

The most reliable way to get the vital orthorhombic phase to form is to deposit a capping layer of tungsten or titanium nitride over the top. Luckily, manufacturers already use tungsten for metal vias as well as in transistor electrodes: its use was a factor in the discovery of the ferroelectric form.

The work has gradually accelerated since Qimonda’s initial papers, some of it through a research group at Dresden-based NaMLab that includes engineers from the now defunct former spinout from Infineon Technologies. But this year’s VLSI Technology Symposium saw several groups make progress in working out what makes the biggest difference to hafnium dioxide’s ferroelectricity.

The papers showed how crystal orientation, which is influenced by the state of the surface before deposition, temperature, stress and even styles of operation play a role in how well commercial memories can deliver on retention, speed and endurance. One piece of good news is that ferroelectric hafnium oxides scale more readily than PZT.

Work by Lawrence Berkeley Laboratories several years ago and later backed by other groups, found thinner films can deliver more consistent results and longer endurance than thicker layers. However, endurance with films in the 5 to 10nm range in work by the University of Tokyo presented at VLSI was just 100,000 cycles: far lower than the trillion cycles or more of today’s commercial, though low-density memories.

Part of the problem with endurance is that the memory window, the zone in which reliable switching behaviour takes place, shrinks over time. This seems to be caused by several factors. Like flash memories, the crystal interfaces degrade under the influence of write voltages, though they are smaller than those used in flash memories. But the degradation may not be permanent. Several teams have found they could reverse the effects of the fatigue by applying moderate frequency pulses.

The reason? The pulses help redistribute oxygen vacancies in the lattice. This behaviour may play a role in the reason why thin films seem to perform better: the Tokyo experiments showed that though some interface degradation is permanent, thinner films react better to the recovery pulses.

Removing a hard interface between layers in the stack may boost both retention and endurance. A team from National Taiwan University (NTU) built a ferroelectric transistor (FeFET), by gradually altering the components of a crystal sandwich hafnium and hafnium-zirconium oxides. This boosted endurance to an estimated ten billion cycles, and data retention of around a day. The team believes retention can be increased to 10 years with further changes to the way they form the layers. Performing the process under vacuum may help according to work at the National University of Singapore, as this prevents damaging oxygen traps from forming.

Subtilities of interface chemisty

Improvements in the understanding of interface physics are not just helping FeRAM out of its long stay in the doldrums. Other memory technologies are now turning up that rely on subtle characteristics of interface chemistry.

The memory technology developed at the University of Lancaster professor Manus Hayne and colleagues takes advantage of a conduction band that forms in the interfaces between a sandwich of III-V elements.

This lets electrons tunnel to and from a floating gate similar to that used in flash devices but with a much smaller write voltage. The key to the UltraRam design, which has been spun out in the startup Quinas, lies in a sharp interface between the layer and the ability to form layers with a clearly defined thickness.

Although, in the case of Quinas the first parts will made be on a comparatively mature process node and compatible with mainstream production equipment, the new generations of non-volatile memory call for precisely defined layers and interfaces.

For the FeRAMs which are largely aimed at nanometre-class processes, the continuing trends towards atomic-layer deposition, as regular transistor features themselves get thinner and more dependent on fine crystal structure, may favour the transition from existing flash and SRAM to these new memories, especially if they can continue to make good on promises to deliver low-energy switching combined with long endurance and retention times.