In the coming years, Tier 1 automotive suppliers have an enormous opportunity with the development of autonomous vehicles (AVs) but there are challenges - the whole supply chain is being disrupted by new participants and new technologies.

Semiconductor companies and specialist OEMs are now major players and newcomers include both well-established companies and small start-ups.

This will affect the role of tier 1 suppliers, and they will need to adapt to ensure that they continue to add solid value to the supply chain. One important step in that direction is the adoption of new system verification strategies as a response to the increased difficulties posed by vehicles that have to be safe enough to drive themselves.

With AVs the architecture is moving from one containing many small, independent engine control units (ECUs) to a more centralised approach with higher-powered multicore processors running extensive suites of software. This brings new players into the picture, and means that the supplier ecosystem must be reinvented to reflect these new contributions.

Tier 1 suppliers, in particular, will encounter a number of specific new challenges: large technology companies like Google, Amazon, and Baidu may weaken the traditional supply chain by doing things differently; OEMs may work directly with tier 2 semiconductor companies, squeezing out the tier 1 supplier; electric-vehicle start-ups, especially in China, are opening up new markets and may bypass tier 1 suppliers in the process; and some specialist OEMs, like Tesla, are integrating vertically, leaving out the entire traditional supply chain.

This changing environment is forcing all players to rethink their roles in the supply chain. Sticking to old models will decidedly not be a winning strategy. In order to understand where changes and new opportunities lie, we need to understand the implications of this new electronic push within vehicles.

Silicon content is booming

Increased electronics sees more silicon in an autonomous vehicle, and this poses a unique challenge to tier 1 systems designers. There is specific growth in the use of systems-on-chip, or SoCs that are sophisticated, highly integrated chips that include custom computing capability. No SoC can be complete without considering the software that the SoC will execute and this adds a new dimension to silicon verification.

Traditional automotive flows use four different tools for verification. New flows are adding a fifth.

Those traditional flows include:

• Virtual prototypes that leverage high-level models of hardware behaviour. While these models execute quickly, their accuracy is insufficient for full verification.

• Hardware-in-the-loop (HIL) is an option once hardware is available and stable. Because this relies on existing hardware rather than a fully instrumented verification test-bench, stimulus tends to be non-deterministic, and, when things go wrong, debugging is difficult.

• Software simulation provides full cycle accuracy and has excellent debug capabilities, but it runs far too slowly for full verification coverage of both hardware and software in an SoC or a system-of-systems. Testing software may mean first booting an operating system before testing how drivers interact both with the silicon and that operating system and involves millions of cycles of execution.

• Hardware prototyping options lack the capacity, debug visibility, and design-change turnaround time necessary for full-chip and system-of-systems verification.

New on the scene are digital-twin representations of vehicles, modelling not just the silicon, but all aspects of a vehicle. These represent an increasingly important component of vehicle verification and validation strategies and represent a significant computing challenge.

Given the amount of heavy lifting that silicon will perform in vehicles and the enormous cost of having to redo a silicon chip, full verification must be completed before chips are produced, creating a pre-silicon verification gap. Bridging that gap is critical - verification must include not just the silicon in isolation, but the ways in which the silicon interacts with the rest of the vehicle.

PAVE360 and Veloce

Siemens’ PAVE360 programme was created for automotive design. Playing a central role is the Veloce emulation platform for verification and validation of automotive electronics and subsystems – an emulator is a special-purpose supercomputer that models integrated circuits before they’re built.

Because it uses hardware instead of software to do the modelling, it can run 100-10,000 times faster than software simulation can and it’s a full-on computing environment dedicated to simplifying specific verification tasks.

While new to automotive electronics, emulators have long proved their worth in verifying complex SoCs for the telecommunications, storage, and mobile markets.

Emulation is the only way to thoroughly verify an SoC and as SoCs move into vehicles, emulation becomes a necessary automotive verification tool.

It allows connection to virtualised data sources to be used as test stimulus. By virtualising these sources rather than relying on real-world sources, the test data is deterministic and repeatable, speeding up debug and resolution of any issues found during verification.

Full verification involves more than just exercising functionality. It’s important to confirm that power doesn’t exceed its budget.

Safety must be verified and documented in accordance with the ISO 26262 safety standard. Silicon chips have internal test infrastructure (design-for-test, or DFT), and those circuits must be verified. All of these tests contribute to the overall verification coverage – that must be tracked and reported.

These are the specific tasks performed by the software applications that run on Veloce emulators. Those applications abstract the implementation specifics of the tests, allowing verification engineers to work at a higher level with greater productivity.

Emulators also provide a way to verify that those SoCs and other chips correctly interact with the mechanical components they control. Those components rely on tools and methodologies different from those used in silicon design.

PAVE360 brings these tools together using standard electronic and automotive interfaces like transaction-level modelling (TLM), part of the IEEE SystemC standard used by the Vista verification tools, and the functional mock-up interface (FMI), used for interactions between electronic and mechanical tools.

Finally, digital twins require maintenance of a digital model of a system in synch with a real version. That means modelling all of the electronic content and coordinating that with a full set of mechanical models. Emulators are the only means of handling such a large computing task in a meaningful timeframe.

Verification of new automotive designs has become much more complex due to the integration of electronics and mechanical components. As electronics pervade autonomous vehicles, silicon must be verified in conjunction with all of the non-electronic parts of the vehicle. SoCs must have both their hardware and their software thoroughly vetted. And digital twins must be built and exercised. Early pre-silicon verification means that the first chips built will be correct, avoiding lengthy and expensive re-spins.

Tier 1 companies belong at the centre of this verification effort, pulling together all of the components and subsystems into one coherent model. It’s a job that’s easy to get wrong without the right tools, and yet, done right, it lets tier 1 suppliers add value and differentiate.

There’s no practical way to achieve this without PAVE360 and emulation. By adopting this new-to-automotive methodology, tier 1 suppliers reinforce their value in the supply chain, partnering across the ecosystem as well as up and down the value chain.

By adapting to these new realities tier 1s can ensure they remain a critical, valued part of the automotive supply chain.

Author details: Richard Pugh is a Product Marketing Manager in the Emulation Division at Mentor, a Siemens business