Featuring best-in-class dynamic range with low power consumption, the ADC3660 family includes eight SAR ADCs in 14-, 16- and 18-bit resolution at sampling speeds ranging from 10 to 125 MSPS, helping designers improve signal resolution, extend battery life and strengthen system protection.
In a high-speed digital control loop, the ADC acts in a complex system to respond to fast changes in voltage or current to help prevent costly damage to critical components in power-management systems and its is becoming more important for the system to make quick decisions to prevent system failure, requiring higher precision at faster speeds.
Using the ADC3660 family, system designers can achieve one-clock (8 ns) ADC latency with the 125-MSPS, 14-bit, dual-channel ADC3664. The family’s ultra-low latency enables high-speed digital control loops in a wide variety of industrial systems to more accurately monitor and respond to voltage and current spikes, increasing tool precision in applications such as semiconductor manufacturing systems.
Up until now, engineers designing industrial systems had to choose between excellent noise performance and low power consumption. The ADC3660 family eliminates this trade-off.
For example, the ADC3683 improves noise performance in narrowband-frequency applications such as portable defence radios, offering a signal-to-noise ratio (SNR) of 84.2 dB and a noise spectral density of -160 dBFS/Hz while maintaining low power consumption of 94 mW per channel.
The ADC3660 family’s high sampling speeds and integrated features help designers reduce the number of components in their systems. The ADC3683, for example, which samples four times faster than competing 18-bit devices at twice the channel density enables oversampling, a technique that pushes harmonics further from the desired signal. This allows designers to reduce antialiasing filter complexity and system component count by as much as 75%.
Other features that reduce design complexity include on-chip decimation options that enable designers to easily remove unwanted noise and harmonics in the system and boost SNR and spurious-free dynamic range up to 15 dB. These decimation options, along with the complementary metal-oxide semiconductor (CMOS) interface, enable designers to use these ADCs with Arm-based processors or digital signal processors instead of field-programmable gate arrays (FPGAs), which can help lower system cost.
Additionally, an integrated digital downconverter with a complex numerically controlled oscillator reduces the amount of processor resources required.