Incorporating rapid prototype technology from the Cadence Genus Synthesis Solution engine, it is said the Joules RTL Power Solution can analyse designs of up to 20 million instances overnight with gate-level accuracy within 15% of final power as signed off in the Cadence Voltus IC Power Integrity Solution. In addition, the Power Solution integrates with the Cadence Palladium emulation platform and the Stratus High-Level Synthesis (HLS) platform for early system-level power analysis and optimisation.
The device also features adjustable power analysis resolution, meaning power-critical frames of a simulation can be zoomed in on and multiple stimulus files for different design hierarchies can be merged to mimic full SoC traffic and power consumption. Advanced data mining and debug enables power to be reported at the bit level or register level and may be categorised based on logic cell type, design hierarchy, clock domain, power domain, or timing mode.
A suite of library analysis and profiling tools is also included.
