Outlook 2015: The next wave of verification innovation

5 mins read

The current growth of the mobile and IOT markets is driving a new wave of even more complex SoCs with large software content, intensifying schedule pressure as development teams push existing verification solutions to their limits.

Increased verification requirements for complex, software-centric SoCs often lead to higher development cost, delayed time-to-market, or both. In fact, a recent analyst report found 'Verification cost represents the largest cost category...software verification costs are higher than hardware verification costs for most system SoC products. The need to develop and fully verify the software can be a key factor in how rapidly new products can be brought to the market.1 We hear similar sentiments directly from system and semiconductor market leaders and are working closely with them to define new approaches to verification for this new generation of complex, software-centric SoC. Driven by chip complexity The industry has solved similar challenges in the past when chip complexity strained the capabilities of existing verification technology. In the 1980s, gate-level design and verification gave way to register-transfer level (RTL) design and simulation using the Verilog and VHDL languages as chip developers demanded higher levels of abstraction. By the next decade, increasing demand for performance led to compiled-mode simulators and other algorithmic optimisations for dramatic improvements in simulation performance. By the 2000s, a number of new 'bug finding' technologies emerged – such as assertions, advanced testbench and coverage analysis – which connected to RTL simulators to improve productivity. However, these 'bolt-on' tools often resulted in slower simulation performance, and many new languages for engineers to learn. Recognising the need for a new approach, Synopsys led the industry to integrate these technologies into the simulator for higher performance and collaborated with leading customers and other vendors to introduce SystemVerilog as the industry-standard design and verification language. Verification demands for today's complex, software-centric SoCs, coupled with shrinking market windows and time-to-market pressure, are driving leading IC developers to look for solutions to help 'shift-left' their schedules – that is moving verification tasks to earlier in the cycle in order to start software bring-up earlier and complete verification sooner. Let's take a closer look. Verification discontinuities Verification requires many different engines for different parts of the IP and SoC verification flow. At the earliest stages of the design, developers may employ virtual prototyping for architecture exploration and early software development. As RTL becomes available, a variety of static, formal and simulation technologies are deployed to find and eliminate design bugs. As the RTL matures, verification teams often migrate their design to a high-performance emulator for long SoC verification tests and early software bring-up. Finally, they may move the design to an FPGA-based prototype to provide the performance required for software development and system validation with real-world interfaces. With each of these verification steps, engineers face the challenge of 'bringing up' a design on the next engine. It can be a very complex, difficult and time-consuming process. Each engine may support or interpret RTL slightly differently or have some other incompatibility, requiring changes to the RTL or supporting collateral. These verification discontinuities – from static/formal to simulation, from simulation to emulation, from emulation to prototyping – can add weeks or months to the schedule and introduce risk, given the manual design changes that are sometimes needed. Debug presents another major challenge. As a design progresses from simulation to emulation to prototyping, each engine provides a higher level of verification performance. However, each step in this progression also provides decreased debug visibility – if a bug is encountered, it is more difficult to diagnose and fix. Engineers must often move the design back to an earlier engine – from prototype to emulator or from emulator to simulator – to localise and correct the bug. The initial design bring-up challenge is experienced again, this time in reverse, and engineers must often go to extraordinary lengths to reproduce the bug on the other engine. These debug discontinuities can introduce even more delay, often at a critical point near the end of the chip development schedule. Looking to 'shift-left' We have collaborated closely over many years with market-leading companies to understand the verification requirements for their next-generation chips, leading to advances in verification that have since become mainstream. Today we are seeing a new set of requirements from these market leaders who are looking to 'shift-left' their verification timelines. What we've heard can be summarised in four key requirements: • Fastest engines Performance has been, and continues to be, the top requirement for verification teams. Each engine in the flow, including virtual prototyping, static and formal verification, simulation, emulation and FGPA-based prototyping, must be best-in-class in terms of performance. • Unified compile Simulation continues to be the cornerstone of verification and customers want their compile flow to be built around the leading simulation engine, proven on complex chips. Most of today's most complex chips are verified with Synopsys' VCS simulation environment. Once a design has been compiled for simulation, it should be seamless to bring up the design in emulation or FPGA-based prototyping. Language support should be consistent, execution semantics the same, compile scripts common. So compatibility with VCS is critical to the success of such continuum. • Unified debug Up to 50% of verification time is spent in debug, and engineers want to use the most popular and productive debug environment available throughout the flow. Today, Synopsys' Verdi debug solution is used in most design and verification flows. Verdi's open environment also allows users to use all simulation, emulation, and formal solutions. As a design moves between engines, the debug environment and database should be consistent, enabling debug to proceed fluidly between engines and abstraction levels, and across both hardware and software. Verdi's open and extensible platform enables teams to pursue further customisation and productivity innovation. • Support for FPGA-based emulation and prototyping Leading semiconductor developers have concluded that FPGA-based emulation is the best choice today and in the future, providing enduring performance, refresh-rate and cost/scalability benefits compared with emulators based on custom chips. To take advantage of these benefits, the verification flow must be architected to take full advantage of FPGA-based hardware platforms. Synopsys' Verification Continuum Platform Over the past two years, Synopsys has brought together the industry's fastest verification engines and has made significant R&D investments to create a unified compile and debug environment across the verification flow. We call this the Synopsys Verification Continuum platform and recently unveiled it to enable the next wave of innovation in early software bring-up for complex SoCs. Synopsys has a track record of leading the industry in key verification transformations – going back to single compiler technology for simulation, assertions, testbench; the creation and widespread adoption of SystemVerilog; and, more recently, the introduction of our Verification Compiler product. This was the first step toward enabling an industry transformation, whereby multiple verification software capabilities, verification IP and debug were brought together in a single product to deliver performance and productivity improvements. Our Verification Continuum platform completes this picture, defining how we and our leading customers will enable 'shift-left' for earlier software bring-up on complex SoC. An industry transition doesn't happen overnight. It requires a solid foundation and a development path that makes the shift from an industry focus on individual point tools and engines to a seamless high-performance platform, something that industry leaders recognise as critical to ensuring the most complex, software-centric SoCs can be developed and brought to market as quickly as possible. 1: Global System IC Industry Service Report, July 2014, International Business Strategies, Inc. Synopsys Synopsys provides products and services that accelerate innovation in the global electronics market. As a leader in electronic design automation and semiconductor IP, Synopsys' comprehensive, integrated portfolio of system-level, IP, implementation, verification, manufacturing, optical and FPGA solutions helps to address the key challenges designers face such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in quickly bringing the best products to market while reducing costs and schedule risk. For more than 25 years, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems. Manoj Gandhi is senior vice president and general manager of Synopsys' verification group.