Integration issues threaten the development of large scale SoCs and suggest different approaches might be more successful
The tug of war between analogue and digital is entering a new phase as the problems that have faced mixed signal designers for years now threaten the development of large system on chips (SoCs). Robert Hum, general manager of Mentor Graphics' deep submicron division, says: "There is tremendous security if you're in mixed signal design and verification. Some 80% of all SoCs today have analogue functionality. If you are an analogue IP company, you have it made." At the turn of the millennium, the trend was inexorably towards the dense, predominantly digital, SoC. Companies such as National Semiconductor saw the SoC market as a growth driver, sometimes selling off divisions dedicated to simpler analogue parts. Now, the trend has gone into reverse at a number of large chipmakers – companies such as Freescale, NXP and Texas Instruments claim their core strengths lie in 'high performance analogue'. Rich Beyer, president and ceo of Freescale, claims: "We do embedded processing, but what we do differently is that we surround those processors with sensors, rf and analogue." This concentration on analogue integration has attracted traditional mixed signal players such as Maxim, which has bought into SoC makers such as Teridian Semiconductor, a specialist in smart meters, and security chip company Inova Card. The latest design to come out of the Teridian operation, according to Bart DeCanne, business director for applied converters at Maxim, is a powerline communications ic that employs some 26million transistors. Maxim sees its portfolio of mixed signal parts helping to drive this expanding SoC business. Even those experienced in mixed signal designs face an uphill struggle in getting their chips to work as they integrate more. "The bad news is that, for advanced technology nodes, what used to be third order effects are now fully fledged primary effects," says Hum. "But the analogue design methodology and attendant toolset has not evolved much at all. We seem to be addicted to Spice." Ciaran Whyte, cofounder and cto of design house IC Mask Design, says he expected analogue design to be automated more heavily far sooner. "I started doing analogue layout 15 years ago and Cadence came in with Virtuoso and said it would be completely automated within a few years. Fifteen years later I am still pushing polygons, so the design bottleneck is still there." Because of the need to port analogue IP to a growing range of designs, people such as Whyte expect automation to become more prevalent in mixed signal designs. However, it is likely to take a different tack to the automated circuit generators promoted by electronic design automation (EDA) companies in the past. Early stage startups such as Bristol based Attocad, see a future in automated layout. Faisal Awqati, ceo of Attocad, claims a functional prototype of the Layout Maker tool has been on four different chip projects, slashing the time needed to create circuit layouts. But, unlike digital design, analogue design and the target process technology are linked more intimately. The circuits do not just need to be laid out differently to migrate to a smaller process, they may need to be changed completely. As on chip geometries reduce, so too do voltages, with a knock on effect on analogue performance, says Peter Frith, Wolfson Microelectronics' cto. "Physics says, as the power supply voltage reduces, the more problems you have for analogue. Halving signal swing worsens the analogue signal to noise ratio by 6dB. To halve that noise, we have to reduce the impedance to a quarter, which demands four times the current. So the power consumption doubles." Liesbet van der Perre, director of Belgian research institute Imec's green radios programme, argues that it is possible to deal with reducing voltage headroom and still cut power in rf designs at least, using the Scaldio radio demonstrator as an example. "When people say analogue doesn't scale, we say look at Scaldio over the last three generations. We have been building with fewer passive components, because passives don't scale well." Digital circuitry has also been deployed to help compensate for problems that are too power hungry to deal with in the analogue domain. Frith says one option is to increase the voltage headroom using charge pumps, something that Wolfson has done in headphone amplifiers. "By changing the way we implement the charge pump, we can reduce power dissipation in the amplifier." The alternative, at least in high integration devices, is to use more digital circuitry and restrict the analogue section to an array of a/d and d/a converters. "In the future, every analogue input will be digitised as soon as it enters the chip. There will be no mixing together of analogue signals at all. It will need much more dsp, but the analogue circuitry required goes down all the time," says Frith. However, monolithic SoC integration is only one path open to mixed signal designers. Craig Ochikubo, general manager for wireless personal area networking at Broadcom, says integration is problematic, even in high volume markets such as mobile phones. Although it is relatively straightforward – from a design standpoint – to put a Bluetooth physical interface onto a baseband processor, this is rarely the path taken by silicon suppliers, who choose to put Bluetooth, WiFi and other local radio interfaces onto a 'combo' chip. "The development of the baseband moves at a different pace to connectivity. WiFi and Bluetooth have seen tremendous changes in their standards recently. And, once a baseband integrates, it doesn't have the flexibility for upgrades. "Baseband devices are primarily digital. The large analogue content of connectivity solutions plays better in combo devices. We don't see a lot of migration between the two." The adoption of system in package (SiP) designs by handset makers has helped reduce the cost and improve the prospects for multichip packaging, which until recently have been too expensive to deploy in mass markets. Costs have reduced to the point where it is now practical to use multiple dice, even at the microcontroller level. With this kind of architecture, the digital parts can use the most advanced process available to improve density, while analogue circuits, which do not shrink well with reducing geometry, can use older processes that have better voltage headroom. Earlier this year, Analog Devices introduced a microcontroller that put its a/d converter onto a separate die, packaged alongside the main Blackfin processor. Anders Frederiksen, marketing segment manager for motor control, says the decision to keep the chips separate made it possible to use a 90nm process for the processor 'compared to our competitors, who are at 0.25µm' and dedicate the 0.25µm to the a/d converter. To reduce noise coupling between digital and analogue circuits, the designers placed the dice side by side, rather than stacking them. "Compared to an embedded solution, it is more costly but we can optimise each of the processes," says Frederiksen, adding that the package design lets the company mix and match I/O options more easily. For absolute lowest cost, SoC will prevail. But these designs will demand massive volumes that only markets such as mobile telephony will support. Greater levels of automation and access to 3d packaging will help mixed signal companies work on optimising designs for lower volume markets and avoid a future where they have to produce 'one size fits all' designs forced on them by the economics of deep submicron SoC production.