Tenstorrent and Imperas to provide Ascalon RISC-V Core model

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Imperas Software, a supplier of RISC-V simulation solutions, has announced that a collaboration with Tenstorrent, a next-generation computing company that builds computers for AI, will make available a model of the Tenstorrent Ascalon processor core as part of the Imperas RISC-V model library.

As with other areas of abstraction during the complex SoC design process, software simulation provides a functional representation as a programmer's view of the hardware - this allows an early-stage evaluation of some design options, firmware, and driver development and offers unique access for debugging and analysis.

The Tenstorrent IP model, available as part of Imperas simulation solutions, can support many time-critical aspects of SoC development and help to address the time-to-market and time-to-volume factors for SoC developers adopting Tenstorrent IP.

Ascalon is a high-performance, scalable RISC-V processor with a highly configurable core that allows it to scale from the Edge to HPC data centre/cloud applications.

The Imperas model can match Ascalon's configuration space, including multi and many core options, while offering fast simulation performance for software development of highly complex systems and exploration of different system architectures.

As virtual platforms are now the most common approach to SoC projects with integrated processors, quality reference models need to accurately represent the configurability of the processor IP core. In addition, for software developers and the wider user community adoption, the models must be compatible with various industry-standard tools and design flows.

Many SoC projects are undertaken with teams from multiple locations and often across different corporate departments or even separate firms. Virtual platforms allow for frictionless collaboration across these different teams.

The Imperas model for Ascalon can also integrate within other standard EDA environments, such as SystemC, SystemVerilog, and well-known simulation and emulation tools from Cadence, Siemens EDA, and Synopsys. A hybrid approach is often utilised to combine the Imperas simulation technology with emulation environments to address interim analysis requirements while parts of the RTL of the SoC are still in development.

"The Tenstorrent Ascalon processor is focused on serving the compute requirements of next-generation workloads emerging at the Edge and data centre/cloud with the rapid proliferation of AI high-performance applications, including Edge AI and HPC," said Aniket Saha, VP of Product Strategy at Tenstorrent. "The Imperas model for Ascalon provides a quality model for software development and integration with many popular industry standard flows and EDA tools."

"Any SoC developer that implements an IP processor core quickly discovers the fundamental interactions between the hardware and software design phases," said Simon Davidmann, CEO at Imperas Software Ltd. "Now developers using the Tenstorrent Ascalon IP can use the Imperas models as a reference for software development to support the shift-left of project schedules."

The Imperas models of the Tenstorrent IP core portfolio are available now via www.OVPworld.org.Imperas RISC-V reference models are also available via approved EDA distribution partners.