Barcelona based start up Elastix is aiming to be the first eda provider to automatically generate variability aware asynchronous implementations of synchronous digital ics.

“Variability aware asynchronous designs are ideal for low energy consumption, high performance and ease of architecture and implementation of large chips,” says Vigyan Singhal, Elastix’ ceo. “Implementing asynchronous techniques has required manual design or significant and unacceptable changes to the standard asic design flow, making it an impractical methodology until now.” Elastix says its technology will allow a functionally equivalent asynchronous design to be generated automatically from a synthesisable digital design. The company claims the design vwill work within a traditional asic synchronous design flow The underlying technology has been licensed from Universitat Politecnica de Catalunya Barcelona (UPC).