Socionext introduces 5G direct RF transmitters and receivers

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Socionext, a developer of System-on-Chip (SoC) solutions, has developed a high-speed Direct RF data converter PHY solution.

This is the latest in a series of IP offerings that are intended to drive advanced transceiver systems for 3GPP 5GNR/LTE and Wi-Fi network infrastructure in the FR1 and FR2 (mmWave with external mixers) bands.

The IPs were developed using TSMC’s 7nm FinFET (N7) process technology to allow for a simple integration for 32TRX and 64TRX single die solutions and lower power consumption compared to discrete solutions currently available in the market.

Both ADC and DAC have 12-bit resolution and analogue bandwidth up to 7.2GHz. The ADC sampling rate is 24GS/s and 32GS/s for the DAC, enabling 5GNR FR1 frequency in the first Nyquist data converter frequency range.

This Direct RF IP product family can deliver the full sub-6GHz instantaneous band with an internal capability to allocate up to 1.6GHz of channel bandwidth featuring carrier aggregation.  Maximum is 16 channels of 100MHz (FR1) each, or 4 channels of 400MHz (FR2). In addition, by using the multiple DDC/DUC available in the macros, it is possible to target low-, mid- and high-range bands (e.g., n28, n40 and n78) simultaneously, without dedicated external filtering components. The result is a significantly reduced BOM.

Yutaka Hayashi, Corporate Senior Vice President and Head of BU (Data Center & Networking Business Unit) said, “Socionext’s 7nm Direct RF silicon IPs are available for new product designs and mass production with a guaranteed short time-to-market made possible by Socionext’s global solid post-silicon supply chain. The Direct RF test chip and evaluation board are now sampling to select customers. A dedicated application board with full ADC/DAC and real-time streaming will be available in Q3, 2023”.

The complete Socionext SoC solution includes a foundation of IP building blocks such as short, medium and long reach SerDes up to 112/224Gbps, PCIe Gen4/5/6 PHY, eFPGA, DDR and several standards-based, die-to-die interconnect technologies for managing data flow across the data infrastructure and chiplets on MCM.

This 7nm data-converter development follows numerous successful 16nm and 28nm designs using Socionext’s high-performance ADC and DAC design expertise for networking applications.

Socionext integrates these IPs into other solutions such as 5G CPE, satellite communications, software- defined radio, microwave radio, test & measurement equipment and early 6G research.