SiLabs has universal clock buffers for simplified system design
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Silicon Laboratories has introduced the first universal clock buffers capable of replacing LVPECL, LVDS, CML, HCSL and LVCMOS buffers with a single ic, eliminating the need for multiple fixed format buffers.
The new Si533xx family integrates common clock tree functions including clock distribution, clock mixing, clock division, format translation and level translation.
Based on a patented low phase noise clock driver architecture, the devices offer ultra low additive jitter with guaranteed maximum jitter specifications, and providing designers more jitter margin for other devices.
The Si533xx clock buffers are purpose built to address the requirements of communications, data centre, wireless infrastructure, broadcast video and embedded computing applications.
Mike Petrowski, vice president and general manager of Silicon Labs' timing products, said: "We've applied innovative mixed signal techniques to create an entirely new category of clock buffers specifically designed to address the headaches typically associated with clock tree design.
"The Si533xx family redefines clock buffer functionality by encompassing a high level of integration and universal, any format translation without performance compromises, giving developers greater flexibility to innovate and simplify their system designs."