Christen Decoin, product management director for Cadence’s digital and signoff group, said: “Over the past few years, the design rule count (DRC) has almost doubled with each new process node and the rules have become increasingly complex. Today, DRC iterations are having a significant impact in terms of time to market delays. We have been able to reduce turnaround time from days to just a matter of hours.”
According to Decoin, Pegasus is intended to provide the speed and capacity designers need to speed tapeout times. “Its gigascale processing offers near-linear scalability that we have been able to demonstrate on up to 960 CPUs. It has allowed customers to reduce DRC signoff runtimes dramatically.”
Pegasus can be integrated with Cadence’s Virtuoso design platform, as well as with the Innovus Implementation System.
“Current DRC solutions haven’t been able to support the turnaround requirements needed to ensure that design schedules are met,” said Decoin. “Pegasus provides users with an elastic and flexible computing environment, which can help them complete full-chip signoff DRC on advanced-node designs in hours, rather than days.”
