On paper, PCM has the potential to be a ‘universal memory’; it has the characteristics of DRAM and flash, as well as being scalable. It switches more quickly than flash and doesn’t suffer from flash’s block programming requirements.
Yet the last decade or so has seen only very slow progress towards a viable implementation of the technology. STMicroelectronics said in 2004 that it had made ‘significant progress’. Then, in 2008, Intel and ST said they had begun to ship samples. In 2011, IBM demonstrated 2bit per cell PCM and claimed a ‘big step’ towards practical devices.
With close to 50 years development effort having been expended on PCM, there are many who say that it is ‘tomorrow’s technology – and always will be’. But the latest announcement from IBM suggests the technology is now closer to commercialisation than it has ever been.
PCM works, as the name suggests, by switching a particular material – a chalcogenide glass – between one of two states using heat. The material’s amorphous state represents a 0, while its crystalline state represents a 1.
One of the continuing issues with PCM – and there are a few – relates to this fundamental process; the heat required to flip a memory cell from one state to another is such that it can affect its neighbours. This has meant that research has continued at the 90nm CMOS node, where the cells are far enough apart to not be affected, rather than heading towards the nanometre scale processes used by leading edge digital devices.
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| IBM scientist Nikolaos Papandreou with the 3bit per cell PCM chip |
The change of states can also be used to create multilevel PCM cells by ‘freezing’ the transformation process at appropriate points – so long as you can detect those states reliably.
IBM’s latest announcement includes two developments. Firstly, it has shown what it calls ‘reliable storage and moderate data retention’ of 2bit/cell PCM on a 64k cell array. It has done this at what it says are elevated temperatures and after 1million SET/RESET endurance cycles. The interesting part, however, is that IBM says it has shown that 3bit/cell PCM is ‘feasible’ under similar operating conditions.
Dr Haris Pozidis, manager of non volatile memory research at IBM Research Zurich, noted: “The bit error rate of 1 x 10-4 is acceptable and made possible through two technologies. We have developed a new way to read information that isn’t susceptible to resistance drift, as well as a set of coding and signal processing technologies that adapt the way in which information can be read.
“We can follow variations of levels with temperature, noise and drift, so we can always detect the information with high reliability.”
As part of the work, the memory array was programmed, then subjected to temperatures ranging from 30 to 80°C, including 80°C for one day.
“Combined,” said IBM Fellow Dr Evangelos Eleftheriou, “these advancements address the key challenges of multibit PCM, including drift, variability, temperature sensitivity and endurance cycling.”
Another memory technology with similarly elusive qualities is 3D XPoint; announced in 2015 by Intel and Micron, but which has since largely disappeared from view.
The partners have yet to unveil what technology underlies 3D XPoint. Speculation at the time of the launch suggested it could be an updated PCM, picking up on the Intel/ST work noted above (the two created Numonyx, which was acquired by Micron). But speculation is still all we have.
