Previously, scientists at IBM and other institutes have demonstrated the ability to store 1bit per cell in PCM, but the IBM researchers say they have stored 3bit per cell in a 64k cell array at elevated temperatures and that data has been retained for more than 1million cycles.
“Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash,” said Dr Haris Pozidis, manager of non volatile memory research at IBM Research Zurich, “thus answering one of the grand challenges of our industry. Reaching 3bit per cell is a significant milestone because, at this density, the cost of PCM will be significantly less than DRAM and closer to flash.”
To achieve multibit storage IBM scientists developed two enabling technologies: a set of drift immune cell state metrics; and drift tolerant coding and detection schemes.
The cell state metrics measure a physical property of the PCM cell that remains stable over time, and are thus insensitive to drift, which affects the stability of the cell’s electrical conductivity with time. To provide additional robustness of the stored data, a coding and detection scheme adaptively modifies the level thresholds that detect the cell’s stored data so they follow variations due to temperature. As a result, says the team, the cell state can be read reliably for long periods after the memory is programmed.
The experimental multibit PCM chip consists of a 2 × 2Mcell array with a four bank interleaved architecture. The memory array size is 2 × 1000µm × 800 µm. The PCM cells, based on doped chalcogenide alloy, were integrated into the prototype chip serving as a characterisation vehicle in 90nm CMOS baseline technology.
