Independently developed Verification IP (VIP) plays an important role in any verification plan since RISC-V developers’ interpretation of the specification are best tested against an independent reference. Architectural Validation test suites are, therefore, important for RISC-V to ensure hardware implementations are in line with expectations of the software ecosystem supporting RISC-V.
In May of this year RISC-V International's Architectural Test SIG (formerly the compliance working group) moved to using a Python programme/framework v3.0 to run compliance testing and no longer provides signatures or scripts to run targets against their tests.
As a service to RISC-V processor developers, Imperas has ported the RVI tests to the Imperas test framework and has made them available as part of the Imperas test downloads. This means that all of the Imperas tests and all of the RVI tests can be used from one simple make/bash framework.
“With all the design freedoms that RISC-V offers, verification has never been more important to ensure full ecosystem support for new processor implementations,” said Simon Davidmann, CEO at Imperas Software.
“The best test for a processor is simulation-based testing to verify the interaction between the software programme and the hardware operation. Architectural Validation test suites, while not a complete verification plan, offer the basic confirmation necessary to sustain the ecosystem of software support. We are pleased to offer the latest suites for the key ratified specifications of Vectors, Bit Manipulation and Crypto plus the new Embedded E suite, all for free including commercial use, with riscvOVPsimPlus.”
The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld.
Validation tests for the Vector extension and the privilege PMP (Physical Memory Protection) unit are available to Imperas users and are configured to users’ specific hardware option settings.