IMEC refines chip stacking technology

IMEC has further developed its Cu-Cu bonding process for the manufacture of 3d stacked ics by adding a polymer dielectric layer between the stacked dies to act as glue layer during placement.

This allows separating the stacking process into a die placement (low temperature) and a collective (wafer level) thermocompression bonding step (high temperature) resulting in increased throughput. In an eventual product, says IMEC, the dielectric will provide mechanical stability to the extremely thin top die of the 3d stack in areas with few through Si interconnects. Simultaneously, the dielectric will improve the thermal conductivity through the 3d stack in areas with few interconnects between the dies. According to IMEC, the process has been used to create chains with10,000 through Si vias.