IMEC, partners tape out 3d chip

"We are excited to achieve this milestone in collaboration with our 3d integration partners, including memory suppliers and ic manufacturers," said Pol Marchal, IMEC's principal 3D integration scientist. "This test chip is a significant step for the introduction of 3D technology in dram on logic applications." Etna consists of a 25µm thick logic die on top of which a commercial dram is stacked using through silicon vias (TSVs) and micro bumps. The demonstrator features integrated heaters to test the impact of hotspots on dram refresh times and the chip contains test structures for monitoring thermomechanical stress, ESD hazards, electrical characteristics of TSVs and micro-bumps, and fault models for TSVs. IMEC is manufacturing the logic die in its prototype line, while one of the Belgian research institute's partners will be delivering dram dice. After integration at IMEC, the dram supplier will test the fabricated 3d stack. Following this, two other partners will package the 3D stack using flip chip onto an fbga substrate.