imec pushes the limits of EUV lithography single exposure for Logic N5 metal layers and sense DRAM applications

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The limits of EUV lithography is continuing to be pushed by imec, as it aims to advance the readiness of this technology, with a focus on EUV single exposure of the Logic 5nm process node (N5) metal layers and aggressive dense hole arrays.

imec explains that its approach to enable EUV single patterning at these dimensions is based on the co-optimisation of various lithography enablers. This includes resist materials, stack and post processing, metrology, computational litho and design-technology co-optimisation and an understanding of EUV resist reaction mechanisms and of stochastic effects.

The goal is to impact the technology roadmap and wafer cost of near-term technology nodes for logic and memory.

imec explains that first insertion of EUV lithography in high-volume manufacturing is expected in the critical back-end-of-line metal and via layers of the foundry N7 Logic technology node, with metal pitches in the range of 36–40nm.

Its research focuses on the next node (32nm pitch and below), where various patterning approaches are being considered. imec says its approaches vary in terms of complexity, wafer cost and time to yield and include variations of EUV multipatterning, hybrid EUV and immersion multipatterning and EUV single expose.

imec has previously demonstrated advances in hybrid multipatterning and claims to have revealed various challenges of the more cost-effective EUV single exposure solution. It now believes that, together with its partners, it is showing considerable progress towards enabling these dimensions with EUV single exposure.

imec claims it has demonstrated promising advances, including initial electrical results on EUV single exposure focusing on two primary use cases: logic N5 32nm pitch metal-2 layer and 36nm pitch contact hole arrays.

Different resist materials strategies, including chemically amplified resists, metal-containing resists and sensitizer-based resists have been assessed, imec continues. Particular attention was apparently paid to the resist roughness and to nano-failures, such as nanobridges, broken lines or missing contacts that are induced by the stochastic EUV patterning regime.

imec explains that these stochastic failures are currently limiting the minimum dimensions for single expose EUV, but it has managed to identify the primary dependencies influencing failure.

Various metrology techniques and hybrid strategies has also been employed in an effort to ensure an accurate picture of the reality of stochastics. Imec says it will report on this collective work, demonstrating the performance of various state-of-the-art line-space and contact hole resists.

As resist materials advances alone will likely be insufficient to meet the requirements, imec explains it has also focused on co-optimising the photomask, film stack, EUV exposures and etch towards an integrated patterning flow to achieve full patterning of the structures. It says it did this by using computational lithography techniques, such as optical proximity correction and source mask optimisation, complemented by design-technology co-optimisation to reduce standard library cell areas.

Etch-based post-processing techniques, aimed at smoothing the images after the lithography steps, yields encouraging results for dense features, imec adds. Co-optimisation of these multiple knobs is key to achieving optimised patterning and edge placement error control, it continues.

Greg McIntyre, director of advanced patterning, said: “We feel these are very promising advances towards enabling EUV to reliably achieve single patterning at these aggressive dimensions. This would significantly impact the cost effectiveness of patterning solutions for the next few technology nodes.”