IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain that provides embedded developers with everything they need integrated in one single IDE, including integrated code analysis tools ensuring code quality.
Through its optimisation technology, IAR Embedded Workbench for RISC-V helps developers ensure the application fits the required needs and optimise the utilization of on-board memory.
Version 3.10 of IAR Embedded Workbench for RISC-V supports RV64 RISC-V cores, including several RV64 devices from Andes, Codasip, Microchip, Nuclei and SiFive further extending the toolchain’s support for available RISC-V devices.
In addition, symmetric multicore processing (SMP) is now supported, enabling high-performance debugging of multicore RISC-V devices.
“64-bit support is an important milestone for our investment in the RISC-V technology and ecosystem,” commented Anders Holmberg, CTO, IAR Systems. “RISC-V technology adoption and interest continues to grow, especially in the Asia Pacific region, and we are committed to stay in the forefront when it comes to professional development solutions for building high-quality embedded applications across all industries.”
Along with the development toolchain IAR Embedded Workbench for RISC-V, IAR Systems provides build tools for RISC-V enabling modern and scalable build server topologies for CI/CD pipelines as well as functional safety-certified editions of the toolchain.