Following this agreement, version 2.11 of IAR Embedded Workbench for RISC-V will now support the L30 and L50 processors from Codasip. The L30 and L50 are small and energy-efficient low-power embedded processor cores from Codasip, that are fully customisable and adaptable to the unique needs of a project.
IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain with everything integrated in one single IDE. Through its optimisation technology, IAR Embedded Workbench for RISC-V helps developers ensure the application fits the required needs and optimises the utilization of on-board memory.
“Codasip L30 and L50 RISC-V processors are fully compliant with RISC-V specification allowing customers to choose from a variety of compilation and debug solutions,” said Zdeněk Přikryl, Chief Technology Officer, Codasip. “IAR Systems is a market leader in the embedded space and our processors work flawlessly with IAR Embedded Workbench”.
“The Codasip L30 and L50 are powerful additions to the embedded RISC-V ecosystem,” explained Anders Holmberg, Chief Technology Officer, IAR Systems. “We are committed to supporting both new and existing technology partners, as well as customers in making the most out of their investments in RISC-V by continuously expanding our RISC-V product portfolio."